1. Field of the Invention
The present invention relates to a method and apparatus for translating small voltage continuous signals into large full supply signals while maintaining or restoring a substantially constant duty cycle of approximately 50% to generate a clock signal for clocking integrated circuits.
2. Description of the Prior Art
Many integrated circuits, such as memory devices and microprocessors, require a continuous clock signal having a relatively large voltage swing. Voltage controlled oscillators (VCOs) of various types have been used to generate a main clock on chip for clocking logic. Either differential oscillator signals or single-ended oscillator signals are used. The signals within an oscillator usually have swings of fairly small magnitude, typically 100 mV to 1 volt. This low voltage oscillating signal must be translated or converted from the small swing to a large swing for driving complementary metal oxide semiconductor (CMOS) logic. Also, the translator should generally maintain a constant duty cycle of approximately 50%. The ideal 50% duty cycle goal allows for maximum timing flexibility within the logic.
An inherent problem with known voltage translator arrangements is an unsymmetrical path for generating a high versus a low output signal. This asymmetry problem causes a deviation from an ideal duty cycle of 50%. In general, disadvantages of known clock signal generating circuit arrangements include their complexity, the large circuit space required and the difficulty and expense of manufacture.